1. Field of the Invention
The present invention relates to a processor, and more particularly, to a processor capable of managing power consumption.
2. Description of the Related Art
Generally, methods for controlling a system supply voltage or for controlling a clock frequency are used for reducing power consumption in systems requiring minimized power consumption. In this case, a dynamic current according to the clock frequency is reduced and thus the power consumption is also effectively reduced. However, power consumption caused by a static current due to a power supply voltage or a leakage current cannot be reduced.
To reduce the wasteful leakage current, a power-gating technique is used for directly cutting off power. However, the power-gating technique requires a wake-up operation and exhibits a wake-up latency. The wake-up operation is an operation that makes the processor return to a normal mode from a sleep mode, and the wake-up latency is a time that is taken to finish the wake-up operation. After power is restored, a sufficient recovery time must elapse before the processor enters a state in which a stable operation can be secured. During the recovery time, all operations have to be stopped. In addition, even when switching to a sleep mode, power cannot be cut off until pipeline instructions are all finished. In this case, power has to be supplied until completing an operation of a pipeline corresponding to a stage that executes the last instruction. Consequently, power is unnecessarily supplied to circuits that do not execute the instruction and the static current is unnecessarily consumed.
FIG. 1 is a block diagram of sequential stages that execute instructions in a conventional microprocessor and, in the context thereof, a conventional method of cutting off power will be discussed.
Referring to FIG. 1, the conventional microprocessor includes instruction processing stages (stage 1, stage 2, etc.) and a power switching unit 20. Each of the power switches (P1, P2, etc.) within the unit 20 is configured with a transistor as a logic circuit for each of the instruction processing stages. When switching to a normal mode from a sleep mode or vice versa, power is managed by collectively controlling the power switches in the circuits of all stages.
A reference numeral 10 represents sequential stages of instruction execution in the conventional microprocessor. The execution of the sequential instructions includes a fetch stage for fetching the instructions from a memory (not shown), a decode stage for decoding the instructions, an issue stage for issuing the instructions, an execute stage for executing the instructions, and a write-back stage for writing the execution result data. However, since each of the stages can be added or omitted according to designs of the microprocessor, a detailed description thereof will be omitted for the sake of convenience. It should be noted that the processing of the instructions are classified into temporal divisions and logic blocks responsible for operations according to time in execution of instructions. Additionally, there are power switches corresponding to the divided logic blocks. In FIG. 1, these detailed operations of the stages are omitted and five stages are provided to categorize temporal divisions for sequential instruction execution. It will be apparent to those skilled in the art that the conventional operations of instruction execution and stage divisions in the processor are not limited to the drawing.
Again, the power switching unit 20 includes the transistors for supplying power to the corresponding stages. As shown in FIG. 1, the conventional power switch is provided to collectively supply and cut off power to the corresponding circuit of the stages. When switching to a sleep mode, a power control circuit 30, which will be described later, cuts off power to the logic circuits corresponding to all of the stages in their respective entirety only after operations by the final stage 5 have been completed. Additionally, when returning to a normal mode from a sleep mode, the power control circuit 30 simultaneously supplies power to the logic circuits corresponding to all of the stages in their respective entireties.
The power control circuit 30 controls the all of the switches P1, . . . , P5 collectively to supply power simultaneously, or collectively to cut off power simultaneously.
Considering the above configuration, the operation of the logic circuit corresponding to each stage and termination of pipeline instruction execution occur sequentially.